IO Methodology SimDE
SimDE™ from IO Methodology offers significant time savings by automatically creating and validating accurate IBIS models for high speed IC components. Signal integrity engineers use IBIS models to accurately simulate and resolve potential signal integrity and performance issues prior to component availability.
SimDE™ includes a graphical interface for mapping the SPICE buffer nodes as well as using the schematic type editing mode for other nodes settings. It automatically runs SPICE simulations to extract the buffer's behaviour from the Spice buffer. There is no need for manual editing during the process.
SimDE™ has a seamless validation process for IBIS buffer model generation. It remembers all the settings for the SPICE model used when generating the IBIS buffer and uses them for your IBIS model validation on your own topologies. It also provides a detailed DPI (Differential Peak Index) and DAI (Differential Average Index), and reports any differences between the Spice and IBIS buffer simulations as well as the visual waveform inspection.
SimDE™ contains:
- Automatic Spice buffer node mapping capability
- Graphical node setting capability
- Automatic Spice to IBIS buffer extraction process
- Auto Die-Capacitance extraction option for both driving and receiving mode.
- Capable for All IBIS Input / Output / IO model types and differential buffers (Pseudo, half and true differential pair) extractions
- Easy setup for Typical / Minimum / Maximum corner extractions
- The best behavioural curve representation algorithm built-in
- Built-in IBIS standard buffer test fixtures and IBIS validation simulator
- Supports HSpice, Spectre, Eldo, MSIM and TISpice3 integrations
- Extraction using existing data for IBIS and IBIS differential models
- IBIS 5.0 PDN feature auto-extractions
- IBIS buffer model validation sheet with freedom of topology settings
- Detail validation reports with Differential Peak Index (DPI) and Differential Average Index (DAI)
- IBIS buffer curves visual inspection and report for On-die termination, non-monotonic and load-line crossing verification. (SignalMeth™ IBIS Application Module)
- Ease-of-use IBIS File generation wizard with Model Selector Builder
- Customizable stimulus settings for more accurate IBIS buffer model development
IO Methodology provides a fast, accurate, cost effective, way of creating IBIS models for component manufacturers & IP providers. IBIS models help reduce time to market for end users by enabling PCB manufacture prior to component availability. Accurate IBIS models also help reduce PCB re-spins due to signal integrity and performance issues.