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Tech Notes (TN) are short,
single-page technical papers to assist in performing regular tasks
or overcoming some obstacles.
Application Notes (AN) are more
detailed technical papers offering guidance and ideas as to how you might improve the effectiveness with which you use our tools in the implementation of your
designs, in more depth than you get with a Tech Note.
Whilst we make every endeavour to ensure the correctness of the information herein you should verify its suitability for use
in your design as Saros Technology can accept no liability for any damages arising from its use howsoever caused. All
our outgoing email is scanned for Viruses, using Kaspersky
Antivirus, but we do recommend that all downloaded files are
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To register for automatic updates
from Mentor Graphics for their HDL product family: HDL Designer
Series™, ModelSim®, LeonardoSpectrum™, Precision
Synthesis™ and FPGA Advantage®, please register for HDL Informant.
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HDL Designer Series (HDS)
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TN
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AN
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Using Vendor Libraries with HDL Designer Series
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SAN034
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HDL Text and Graphics Import to HDL Designer
Series
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SAN037
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HTML Export from the HDL Designer/Detective
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SAN040
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Version Management and its application in HDL Designer Series
(2003 onwards)
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version_mgmt_v3
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Tips, Tricks and Shortcuts for using HDS
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TN001
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Using Microsoft Visual Source Safe
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vss2
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Precision Synthesis
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TN
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AN
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Precision Synthesis - Xilinx LogiCORE PCI Core
Flow
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PCIcore
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Leonardo Spectrum to Precision Transition Guide
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ls_precision
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Precision RTL Synthesis supports clock
propagation across PLLs
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rtl_clock
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Bottom-up Physical Design - Tools and
Operation
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bottomup
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Leonardo Spectrum
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TN
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AN
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Use of Synthesis Timing Constraints within
Leonardo Spectrum
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SAN007
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Design Analysis with Leonardo Insight
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LeoInsight
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ModelSim
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TN
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AN
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ModelSim 6.3 Platform Support
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modelsim_63_ps
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Compiling (Vendor) Libraries for ModelSim
5.x
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SAN009
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ModelTech's Application Notes
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MGC
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Verifying the quality of your testbench using
Code Coverage
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code_coverage
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Comparing PSL to the OVL or
Proprietary Property Checking Tools
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comparingPSL
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Solutions to Common ModelSim errors
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TN002
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ModelSim Release Dates
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TN003
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ModelSim PE and the Swift Interface
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TN004
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Miscellaneous
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TN
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AN
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Quick License Setup Guide
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SAN002
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Installing ModelSim, HDL Designer Series
and Precision under Redhat Linux
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SAN006
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IP Reuse for FPGA Design
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reuse
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Install or Update Mentor Graphics Licensing (FlexNet
v10.8)
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Mentor
mg66951
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Install or Update Dongle Licensing on Windows (FlexLM
v9.5)
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TN005
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Introduction to Mentor Graphics Licensing on
Unix (FlexLM v8.2)
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1223
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Introduction to Mentor Graphics Licensing on
Windows (FlexLM v8.2)
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1224
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FPGA Vendor Specific
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TN
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AN
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Using Xilinx Unisims within HDS
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SAN044
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Language Specific
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TN
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AN
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Comparing PSL to the OVL or
Proprietary Property Checking Tools
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comparingPSL
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Useful Web Links
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KPP
- A VHDL Pre-Processor: Allows Verilog-style conditional statements
to be used in VHDL
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Accellera:
International development of HDL design standards
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SystemC: The
Open SystemC Initiative (OSCI)
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Opencores:
Free open source IP cores and chip design
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The Free-IP
Project : ASIC and FPGA Cores for the Masses
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