IO Designer

 

A major growing complaint in the FPGA and PCB design worlds is how to control the interface between the two.  Changing pinout definitions as designs are re- placed and routed or as PCB design limitations become apparent has traditionally been handled informally or through the use of spreadsheets and a bit of over-the-wall engineering once the design has been placed and routed.  Until now this has often been considered a minor inconvenience but with the high pin count FPGAs that are now becoming available the flow of information is becoming more critical errors more frequent and the process more costly.

 

    Click here for

·         Datasheet [pdf]

·         More information

·         Success Story [pdf]

I/O Designer offers a unique process for moving between the FPGA and PCB design flows from the top level HDL description to the PCB level symbol as well as to the interface timing for the synthesis tool and the physical pin information necessary for the FPGA place and route tools.  Many of the capabilities offered by IO Designer are intended to remove a large number of the issues and misunderstandings that are often found between the two camps.

 

 

Product Highlights

  • Provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB
  • Focused on optimising system performance, designer productivity and reducing product manufacturing costs
  • Eliminates the barriers between FPGA and PCB flows and design organisations

 

IO Designer Features

For the FPGA Designer

  • Export the top level ports and initial pin placement information from the HDL without having to worry about spreadsheets etc
  • Define pin types – LVCMOS, LVPECL etc, automatically ensuring LVPECL pin pairs for example are placed together
  • Update pin placement information for FPGA to meet timing
  • Constrain pins to certain banks for IO integrity
  • Plug in to your existing FPGA Advantage or HDL Designer flow.

For the PCB Engineer

  • Extract any modifications from the PCB Layout to update FPGA pin placement information
  • Define signal propagation requirements and therefore FPGA-internal routing targets
  • Ensure high-speed parallel bus pins are placed logically close together to minimise track lengths.
  • Ensure pin compatibility with different devices in the family for later functionality additions or cost reduction.
  • Generate symbols in a variety of ways for the PCB/Layout tool

 

IO Designer Flow

 

IO Designer Benefits

  • Provides a graphical IO design environment for both the FPGA and PCB Engineer to guaranty and maintain the consistency between the FPGA and PCB environments
  • Reduces the total product design cycle time by changing a serial process into a concurrent process
  • Eliminates error prone manual tasks
  • Manages and supports pin swaps and their back annotations.
  • Makes achieving high-speed constraints possible
  • Automatic FPGA symbol generation tool with parts library for Actel, Altera and Xilinx eliminating the costs associated with creating and maintaining the FPGA symbol(s) for the PCB schematic
  • Automatically detects changes in FPGA/HDL design, synthesis and Place and Route, or PCB design related files
  • Facilitates migration to larger or smaller devices without a board re-spin
  • Can reduce PCB manufacturing costs by eliminating PCB signal layers and PCB re-spins due to bad FPGA symbols
  • Available on Windows, Linux and Solaris

 

Further Information on IO Designer

To view or download the datasheet, please click here

For more information on IO Designer please contact Saros or call us on 01491 837787.

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