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QuestaSim
- Advanced Verification Environment
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Questa is Mentor Graphics' Advanced
Verification Environment. This is designed to improve quality,
productivity and predictability for any verification flow.
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Click here for
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Benefits
- Standards-based solution to support all
flows, secure your verification investment and enable
interoperability
- High-performance solution built on the
best-in-class ModelSim simulator which supports VHDL,
SystemVerilog, Verilog, SystemC, and PSL
- Support for SystemVerilog and PSL
assertions for improving quality
- Support for SystemVerilog
constrained-random functionality for improving productivity
- Support for SystemVerilog and PSL
coverage-driven verification for improving predictability
- Works seamlessly with VHDL designs
The product range is split up into two
distinct products
- Questa SV (SystemVerilog)
- Questa AFV (Advanced Functional
Verification)
A brief overview of these two products
is shown below, with the differences highlighted:
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Functionality
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SV (SystemVerilog)
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AFV (Advanced Functional
Verification)
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Simulation Environment
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As ModelSim SE
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As ModelSim SE
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HDL Languages
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Verilog, SystemVerilog (VHDL Optional)
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Verilog, SystemVerilog + VHDL
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Assertion Languages
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SystemVerilog
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SystemVerilog + PSL
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SystemC 2.1 Support
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Optional
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Yes
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Debugging
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As ModelSim SE
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As ModelSim SE
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Code Coverage
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Yes
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Yes
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Functional Coverage
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SystemVerilog
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SystemVerilog + PSL
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Platform Support
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As ModelSim SE
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As ModelSim SE
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More detailed comparison information can be found in the
Datasheets and Comparison Chart above.
Online
Demos Available
Note: Registration of contact details is required to access these
online demos
For
more information or to discuss evaluating QuestaSim please contact Saros
by e-mail or call us on +44 (0)1491 837787.
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