Solidify from Averant offers state of the art static functional verification. The underlying technology is mature, having been employed on many production designs over the last six years. Solidify is feature-rich, powerful, and flexible, allowing use by both design and verification engineers. It offers capabilities for both novice and expert users, and complements existing verfication environments.

Solidify features include:

• High-performance engines
• Source-code debugging
• Hierarchical verification
• Memory model generation
• Property code coverage
• Automatic design checks

Supported languages:

• Verilog / VHDL
• SVA, PSL, OVA, OVL

Outputs:

• Property analysis results
• Debug tracing & waveforms
• Testbench generation
• Simulation monitor generation
• Coverage reporting

The concise and comprehensive nature of Properties make a static verification environment extremely effective. In addition our unique Property Coverage module helps ensure that a sufficient number of Properties have been written to fully test the design. The exhaustive nature of formal verification makes it easy to catch both simple bugs early in the design cycle as well as exposing subtle bugs and corner cases.

Solidify is a powerful tool for increasing design quality, reducing verification time, and minimising costs.