Verification Tools

HDL Design Rule Checkers allow you to quickly locate any areas of your design's source-code that do not comply with the coding guidelines required by your project or company standards.

Simulation and Simulation-based Verification

RTL and Gate-level Simulation have been essential in the verification flow since the dawn of the digital design era. Modern simulators include support for Assertion-Based Verification (ABV) languages to maintain a workable level of observability as design sizes increase, and system level modelling languages to help create ever more complex modelling environments.

Static Functional Verification

Static verification tools take assertions or properties as their input and use formal techniques to either prove your design always behaves as it should, or provide an example of it failing. There is no stimulus to write, and no waiting for simulation. When you need to be certain your design works, there is no better approach for verification at the block level.

AMBA Protocol Checking

Formal verification techniques are particularly well suited to the task of protocol verification. This product combines the AHB, APB and AXI protocol rules developed by ARM, a formal engine, and a dedicated easy to use GUI to automate the previously arduous task of protocol compliance checking.

AutoChecks

Formal verification techniques are also particularly well suited to the task of autochecks of code. This product combines the basic checks required to ascertain code correctness, with the Solidify formal engine, and a dedicated easy to use GUI to automate the process.

ASIC Prototyping System

This is a versatile multi-FPGA motherboard built specifically for ASIC prototyping, HW/SW co-verification, proof-of-concept studies and end-user evaluations. It is of modular design and can easily be expanded to support multi-million ASIC gate designs, in excess of 200MHz.

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