The WiCkeD tool suite from MunEDA provides powerful EDA software tools for the analysis, modeling, performance enhancement, and yield optimization of analogue, mixed-signal and digital ASIC designs. Starting from the transistor level design schematic, and fully integrated with leading analogue design frameworks such as Cadence Virtuoso & Mentor Graphics IC Studio, MunEDA’s unique algorithms and optimization modules offer:
- Automatic parameter setup
- Constraint and Feasibility optimization
- Nominal Performance Optimisation
- Yield and Mismatch Analysis
- Yield Optimisation and Design Centering
At the end of the optimization process the WiCkeD tools output an optimised transistor level schematic in which all transistors have been correctly sized. The circuit is now ready for layout.
For more information about MunEDA’s design analysis, modeling and optimization tools please read the attached WiCkeD Tools Overview document.
The WiCkeD tool suite was first released in 2002, and is currently used by many of the world’s top semiconductor companies. We also have many customer circuit reference cases detailing how our customers have used the WiCkeD tools in their work.
Pierluigi Daglio, NVM AMS Flows & Methods Manager, STMicroelectronics:
"WiCkeD is a perfect tool for circuit analysis, design optimization and yield enhancement. STMicroelectronics has used WiCkeD based on Mentor Eldo circuit simulation in numerous benchmarks and real applications and proved it helps to design more robust circuits with a better yield."
MunEDA’s unique algorithms for automatic yield enhancement and circuit robustness can improve the area and yield of analogue designs. This saves costly re-spins, which in turn reduces development costs, shortens time to market, and ensures that the lowest possible per-die fabrication costs are achieved.