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Questa Increase Coverage

Flags code coverage items that are difficult to reach using formal techniques and have not been hit in simulation, providing a valuable measure of verification complexity. This helps guide engineers to make designs more easily verifiable.

Exhaustively identifies dead code areas

No matter how many clever directed tests you write or how many random seeds you try, coverage can plateau. Meanwhile, specifying waivers to exclude unused IP configurations can be a tedious and error-prone manual process.

Automate coverage exclusions with Questa Increase Coverage. It identifies and excludes unreachable code across all hierarchy levels, reducing manual effort and helping break through coverage plateaus. Exclusions can then be analyzed and reviewed in the GUI.

Introducing Questa Increase Coverage

Coverage closure is a critical step in IP verification, ensuring all RTL code is exercised before tape-out and reducing the risk of costly silicon defects. While code coverage is widely automated and used as a key quality metric, achieving 100% coverage remains challenging. As designs mature, persistent coverage gaps often emerge, not due to missing tests, but because of inherent design structures and parameterized configurations that create unreachable code.

Traditionally, identifying and waiving these coverage gaps requires time-consuming manual analysis and close collaboration between verification and RTL engineers, making the process costly and error-prone. Questa Increase Coverage addresses this by using formal techniques to automatically identify unreachable code and generate validated exclusions. This reduces manual effort, accelerates coverage closure, and enables teams to focus on meaningful verification rather than repetitive analysis.

Code coverage closure

Questa Increase Coverage is an automatic formal solution for achieving code coverage closure faster. The tool addresses an incontrovertible fact of verification: no matter the combination of techniques used, and even after running an exhaustive battery of tests, some fraction of uncovered code always remains.

Target coverage holes

Questa Increase Coverage automatically traverses your DUT’s state spaces and identifies unreachable areas, enables the user to “waive”/exclude items from future analyses, and pipe all results into a Unified Coverage DataBase (UCDB) for inclusion in Questa Verification IQ analyses and progress reporting.

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FPGA Equivalence Checking

Questa Equivalent FPGA ensures advanced optimizations needed to meet aggressive power, performance & area goals do not change design functionality, ensuring errors aren’t introduced …

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Improve Productivity and Assurance

User-friendly automated formal applications simplify the process of identifying and resolving bugs, eliminating the need for specialized formal expertise.

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Static RTL Issue Hunting

A fully-automatic formal issue hunting app that finds deeply hidden issues due to common RTL coding errors, Inspect makes it possible to eliminate a wide range of issues without a testbench.

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