Precision Synthesis


Provides FPGA vendor-independent logic synthesis, offering reduced time to market, fewer design defects, and superior quality of results. The powerful optimisation engines, context sensitive GUI, and advanced timing algorithms result in faster designs with higher device utilisations.

Precision Synthesis is the industry’s most comprehensive FPGA vendor-independent solution. It offers best-in-class results for performance and area. Precision has tight integration across the Siemens FPGA flow from C++ / SystemC / RTL design through simulation and formal verification to board design.

Introducing the Precision Series

Precision Synthesis solutions provide high-quality Verilog / VHDL / SystemVerilog synthesis for the latest FPGAs, easy-to-use debug and validation environment, comprehensive & user-friendly high-reliability synthesis, and tight integration with Siemens FPGA design solutions.

Complete FPGA Design Flow

Siemens EDA’s FPGA design solutions deliver an integrated FPGA design entry, synthesis, verification, equivalence checking, and PCB design platform that speeds up FPGA designs from creation to board, meeting design QoR goals and system constraint requirements, with Precision Synthesis at its core.

Complete FPGA Design Flow

The Precision product range includes Precision RTL, Precision RTL Plus, and Precision Hi-Rel covering the complete range of synthesis requirements from small FPGA design through to the largest Vertex and Stratix devices.

Precision RTL Logo

Precision RTL

Entry-level FPGA synthesis solution, offers an excellent quality of results, industry - leading Verilog / VHDL / SystemVerilog language support and an FPGA vendor - independent solution.

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Precision RTL Plus Logo

Precision RTL Plus

Flagship FPGA synthesis and validation solution, offer a best-in-class quality of results, breakthrough advantages for commercial and mil - aero applications.

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Precision Hi-Rel Logo

Precision Hi-Rel

Groundbreaking FPGA synthesis solution, offers a comprehensive & user-friendly environment for mitigation of SEUs / SETs in safety-critical & high-reliability applications.

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Key Features and Benefits

  • High-performance, easy-to-use, vendor-independent RTL synthesis solution
  • Supports VHDL, Verilog, SystemVerilog and EDIF language input
  • Powerful RTL and technology schematic viewers
  • Advanced retiming algorithm to improve performance
  • Interactive static-timing analysis quickly performs "what-if" timing analysis scenarios
  • Gated clock conversion and DesignWare support for ASIC prototyping
  • Support for industry standards with SystemVerilog and Synopsys Design Constraints (SDC) format
  • Design Bar guides users step by step through synthesis, analysis, placement and routing
  • Optional Register Retiming algorithm moves registers across logic to improve performance