Precision Synthesis is the industry’s most comprehensive FPGA vendor-independent solution. It offers best-in-class results for performance and area. Precision has tight integration across the Siemens FPGA flow from C++ / SystemC / RTL design through simulation and formal verification to board design.
Introducing the Precision Series
Precision Synthesis solutions provide high-quality Verilog / VHDL / SystemVerilog synthesis for the latest FPGAs, easy-to-use debug and validation environment, comprehensive & user-friendly high-reliability synthesis, and tight integration with Siemens FPGA design solutions.
Complete FPGA Design Flow
Siemens EDA’s FPGA design solutions deliver an integrated FPGA design entry, synthesis, verification, equivalence checking, and PCB design platform that speeds up FPGA designs from creation to board, meeting design QoR goals and system constraint requirements, with Precision Synthesis at its core.
The Precision product range includes Precision RTL, Precision RTL Plus, and Precision Hi-Rel covering the complete range of synthesis requirements from small FPGA design through to the largest Vertex and Stratix devices.
Entry-level FPGA synthesis solution, offers an excellent quality of results, industry - leading Verilog / VHDL / SystemVerilog language support and an FPGA vendor - independent solution.Learn More
Precision RTL Plus
Flagship FPGA synthesis and validation solution, offer a best-in-class quality of results, breakthrough advantages for commercial and mil - aero applications.
Groundbreaking FPGA synthesis solution, offers a comprehensive & user-friendly environment for mitigation of SEUs / SETs in safety-critical & high-reliability applications.Learn More
Key Features and Benefits
- High-performance, easy-to-use, vendor-independent RTL synthesis solution
- Supports VHDL, Verilog, SystemVerilog and EDIF language input
- Powerful RTL and technology schematic viewers
- Advanced retiming algorithm to improve performance
- Interactive static-timing analysis quickly performs "what-if" timing analysis scenarios
- Gated clock conversion and DesignWare support for ASIC prototyping
- Support for industry standards with SystemVerilog and Synopsys Design Constraints (SDC) format
- Design Bar guides users step by step through synthesis, analysis, placement and routing
- Optional Register Retiming algorithm moves registers across logic to improve performance