Questa automates verification and debug of complex SoCs and FPGAs, dramatically increasing productivity and helping companies manage resources more efficiently. Questa best-in-class technologies maximise the effectiveness of verification at the block, subsystem, and system levels.
The Questa Verification Solution
The Questa verification solution is an assemblage of technologies, methodologies, and libraries for modern ASIC and FPGA designs. Questa continues to evolve in response to the growing complexity of SoC designs.
The key to verification success is to decompose the problem and use the best solution for each aspect of the system. This places tremendous importance on the verification plan and the ability to collect metrics throughout the process and across all verification tasks to track progress against the plan, allocate and manage resources efficiently, and identify trends as the project progresses against schedule.
Questa Advanced Simulator
The core simulation and debug engine of the Questa Verification Solution; the advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.
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Questa Design Solutions
Questa Design Solutions is an automated and integrated suite of verification tools that analyses code at the design stage to detect bugs early, where they are cheapest and easiest to fix.
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Questa Formal Verification
The Questa Formal Verification tool complements simulation-based RTL design verification by analysing all possible behaviors of the design to detect any reachable error states.
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Questa Verification Management
A shared platform and environment for comprehensive verification management of design process, tools and data within a scalable, modular solution.
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Questa Verification IP
Questa Verification IP improves quality and reduces schedule times by building protocol and methodology reusable components that support many industry standard interfaces.
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Questa Visualizer
Visualizer is a high-performance, high-capacity context aware debugger that supports a complete logic verification flow, including simulation, emulation, and prototyping.
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- Integrates multiple point tools into flexible, open flows that integrate a broad arsenal of verification solutions
- Decomposes the problem and employs the best solution, such as CDC verification, formal verification or mixed-signal simulation, to resolve it
- Delivers high performance/capacity debug tightly integrated with the Visualizer Debug Environment
- Increases your ability to build a verification plan and collect metrics to track its progress, allocate and manage resources efficiently, and identify trends as the project progresses against schedule