Questa Design Solutions
Overview
Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyses code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.
Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyses code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.
Automated Intent-Focused Verification for Designers
Questa Design Solutions works with you from design creation through completion with a minimal set of additional inputs. Nothing more than RTL is required, except for UPF and basic constraints, when necessary.
Questa Design Solutions Tools
Questa Design Solutions tools are built on a consistent foundation with a common debug and user interface, producing designs that are correct-by-construction, proving designs meet the designer’s intent and the project’s quality requirements, and protecting the design throughout its development.
Questa Lint
Questa Lint provides adaptive, integrated insight to the designer to ensure that the quality requirements and intent are met. Pre-configured methodologies provide immediate, intuitive feedback on design issues.
Questa Clock-Domain Crossing (CDC) Verification
Questa CDC finds errors using structural analysis to detect clock-domains, synchronisers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.
Questa Inspect
A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, Inspect makes it possible to eliminate a wide range of bugs without a testbench.
Questa Check X
Questa Check X is an automated application that exhaustively roots out ‘X’ issues at the RTL-level without a testbench.
Questa Reset-Domain Crossing (RDC) Verification
Questa RDC finds errors using structural analysis to detect asynchronous reset domains, synchronisers and low power structures via the UPF. It then generates assertions to exhaustively prove that the design is clean.
Questa Signoff CDC
Questa Signoff CDC builds on Questa CDC RTL analysis and automatically generates and analyses assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.
The high impact of design issues on projects
Mistakes happen, but finding and fixing issues late in programs increases overall program scope, as well as schedule and resource requirements. Competitive pressures push teams constantly to do more. Functional verification teams face significant challenges to build testbenches quickly, uncover design issues and enable rapid debug. Incomplete or incorrect bug fixes (or even a hurried introduction of new bugs) compound the problem. In addition, there are classes of design bugs that are challenging to catch at all in functional verification.
Efficient, target-adaptable analyses for designers, Questa Design Solutions provides actionable results to enable designers to ensure that their designs meet their intent. These integrated and complementary solutions are built to enable the designer to find issues when they’re cheapest to fix, rather than letting them become expensive for the entire project to address. This improves overall team agility through more efficient design processes, as well as by allowing functional verification, emulation, and validation efforts to focus on the hard-to-find functional system issues.
The Verification Academy
The Verification Academy is a collection of free online courses, focusing on various key aspects of advanced functional verification.
Software for IC Verification
QuestaSim
Simulation and Debug
Combines high performance and capacity simulation with unified advanced debug and functional coverage for the most complete native support of Verilog, SystemVerilog, VHDL, …
Catapult HLS
HLS and Verification
Industry leading C++ / SystemC High-Level Synthesis with Low-Power estimation / optimization. Design checking, code, and functional coverage verification plus formal make HLS more than ….
Questa Inspect
Static RTL Bug Hunting
A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, Inspect makes it possible to eliminate a wide range of bugs without a testbench.
Questa CDC
CDC Verification
Questa CDC finds errors using structural analysis to detect clock-domains, synchronisers, and low power structures via the UPF. It then generates assertions and metastability models for …
Questa Lint
Static RTL Verification
Questa Lint provides adaptive, integrated insight to the designer to ensure that the quality requirements and intent are met. Pre-configured methodologies provide immediate, intuitive feedback …
Veloce proFPGA
Hardware-Assisted Verification
The Veloce proFPGA system architecture offers best-in-class modularity, scalability, flexibility and portability to serve the verification requirements of today’s hardware and software engineers.