Calibre Circuit Verification

OVERVIEW

The Calibre Circuit Verification suite includes Layout vs Schematic (LVS), reliability verification and parasitic extraction. These tools provide sign-off quality results, as well as integration into Siemens EDA and 3rd-party products for circuit simulation and other downstream requirements.



Calibre circuit verification accurately and efficiently addresses functional yield challenges in today's IC designs. The industry-leading Calibre nmLVS tool ensures accurate circuit behavior with precise device parameters, while parasitic extraction tools provide the accurate and high-performance extraction required for all design styles.





Circuit Verification

Calibre circuit verification delivers fast, efficient layout vs schematic and parasitic extraction solutions to ensure circuits will be successful when manufactured. Designers rely on the accuracy of Calibre predictions for silicon performance and reliability to achieve first-time product success.



Calibre nmLVS


The Calibre nmLVS platform delivers high performance layout vs schematic verification, electrical rule checking, and advanced parameter calculation to validate circuit integrity and accuracy.


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Calibre PERC


The Calibre PERC platform is the industry leader for reliability verification solutions, enabling a vast range of IC circuit reliability checks not possible with traditional verification tools.


Datasheet

Calibre xACT


The Calibre xACT tool delivers reference level accuracy for leading edge FinFET, custom, analog, and RF designs, with performance and capacity for multi-million instance digital designs.


Datasheet

Calibre xRC


The Calibre xRC parasitic extraction tool delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. Foundry-qualified for practically every process and node.


Datasheet

Calibre xL


The Calibre xL tool delivers fast, accurate full chip frequency dependent loop inductance and loop resistance extraction that highly correlates with field solvers and provides silicon-tested accuracy.


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Key Features and Benefits

  • The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.
  • Common design platform integration enables rapid deployment of all Calibre nm Platform applications into the user’s design environment.
  • Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.
  • Hyperscaling technology brings superior scalability and lightning fast-run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.