The Calibre nmDRC tool has long led the industry, but today’s designs also demand novel technologies that enable design companies to accelerate time to market and achieve faster innovation. From equation-based DRC to multi-patterning, machine learning, and EDA in the cloud, the Calibre toolsuite provides the proven performance, technology, accuracy, and capacity to handle any design, at any node, at any foundry.
Calibre nmDRC and Calibre nmLVS are the market share leaders in physical verification. Calibre also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of today's nanometer designs.
The market leading layout vs schematic physical verification tool. Tightly linked with Calibre nmDRC and Calibre xRC, it delivers a production proven solution for the physical verification and parasitic extraction of nanometer IC designs.Datasheet
The Calibre nmDRC platform enables reduced cycle time with revolutionary new capabilities that substantially differentiate Calibre nmDRC design rule checking from traditional DRC tools.
Calibre Auto-Waivers technology lets users waive false physical and circuit verification violations to focus on real errors, speed design process, make debug more efficient, and shorten schedules.
Calibre 3DSTACK technology provides comprehensive support for an extensive range of multi-die integration methodologies and processes, including system-level DRC, LVS, and PEX.
The Calibre Interactive interface is the invocation GUI for Calibre physical and circuit verification and parasitic extraction engines, with easy access from within popular layout design environments.
The Calibre RVE results viewer provides fast, flexible, easy-to-use graphical debugging capabilities that minimize your turnaround time and get you to “tapeout-clean” on schedule.
The Calibre DESIGNrev interface speeds full-chip design completions and tape-outs by rapidly loading, displaying, and saving large GDSII and OASIS files.
Calibre RealTime Digital
The Calibre RealTime Digital interface enables on-demand immediate Calibre DRC feedback for digital design flows, enabling P&R engineers to shave weeks off their tapeout schedule.
Key Features and Benefits
- The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.
- Common design platform integration enables rapid deployment of all Calibre nm Platform applications into the user’s design environment.
- Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.
- Hyperscaling technology brings superior scalability and lightning fast-run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.