ModelSim eases the process of finding design defects with an intelligently engineered debug environment.
The ModelSim HDL simulator provides FPGA customers with an easy and cost-effective way to speed up FPGA development and testing. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab, allowing time spent in the lab to be much more productive and focused.
In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.
The ModelSim debug environment efficiently displays design data for analysis and debug of all languages. ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs.
ModelSim shares a common front end and user interface with Mentor's flagship simulator Questa. This allows customers to easily upgrade to Questa should they need higher performance and support for Advanced Verification capabilities.
For advanced verification capabilities such as SystemVerilog class-based testbench, functional coverage, and UVM support, find out more about our highest performance simulation solution: Questa