ModelSim eases the process of finding design defects with an intelligently engineered debug environment.
The ModelSim debug environment efficiently displays design data for analysis and debug of all languages. ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs.
- Unified mixed language simulation engine for ease of use and performance
- Native support of Verilog, SystemVerilog for design, and VHDL, for effective verification of sophisticated design environments
- Fast time-to-debug, easy to use, multi-language debug environment
- Advanced code coverage and analysis tools for fast time to coverage closure
- Interactive and Post-Sim Debug available so same debug environment used for both
- Powerful Waveform Compare for easy analysis of differences and bugs
- Unified Coverage Database with complete interactive and HTML reporting and processing for understanding and debugging coverage throughout your project
- Gain insight and visibility into your design by letting assertions notify you of an error so it can be fixed
- ModelSim provides a powerful library of checkers (OVL) letting you debug with assertions right away, without writing your own
- Assertions can also serve as documentation for your design, as comments are embedded into the code as you go