OneSpin Solutions


OneSpin's solutions enable the most thorough and easiest to use logic verification available. OneSpin’s solutions increase the productivity of design and verification teams, transforming formal verification into a broadly applicable engineering practice.

OneSpin Solutions provides certified IC integrity verification solutions for use across the entire System-on-Chip (SoC) design flow. These solutions assure that designs are functionally correct, safe and meet stringent safety compliance standards, trusted and secure. Its solutions are categorized into four categories:

Design Verification (DV): Rigorous coverage-driven functional verification from block to chip, leveraging unique formal technology.

Equivalence Checking (EC): Automatic detection of systematic design errors introduced by design refinement tools (e.g., synthesis) to exhaustively verify equivalence of RTL to synthesized netlist to final place & route (P&R).

Functional Safety: Safety analysis to meet the strict certification requirements of functional safety standards such as ISO 26262 for automotive, IEC 61508 for industrial, and DO-254 for avionics.

Trust and Security: Automatic detection of RTL Trojans and hardware vulnerabilities to adversary attacks.

OneSpin Solutions

OneSpin's Products

OneSpin provides 2 major product lines, OneSpin 360 DV and OneSpin 360 EC. All products are based on a joint formal platform providing common functionality for design entry, prove engines, debugging, cloud support and programming interfaces.

OneSpin 360 EC-FPGA

360 EC-FPGA solution ensures that advanced FPGA synthesis optimisations do not introduce functional errors.

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OneSpin 360 DV-Inspect

360 DV-Inspect is used to eliminate errors prior to verification or synthesis. The RTL code is targeted using multiple techniques to achieve a rigorous and exhaustive analysis.

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OneSpin 360 DV-Verify

360 DV-Verify is a unified coverage-driven assertion-based verification solution. It is a combination of a fully functional, high-performance formal property analyser with a unique assertion coverage evaluator.

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