360 DV-Inspect

OVERVIEW

OneSpin 360 DV-Inspect takes designers' pain away and automatically and exhaustively analyzes RTL source code prior to functional verification and synthesis, eliminating hard to find implementation errors early in the design process.



Integrated circuit designers are under constant pressure to deliver bug free code that meets evermore rigorous requirements. It is well known that the more bugs that can be detected early in the development process, the faster and easier that development effort will be. However, early bug detection requires a verification overhead on the designer that can be onerous and impact the design process.





Introducing 360 DV-Inspect

OneSpin 360 DV-Inspect helps to rapidly eliminate errors in a piece of RTL, prior to functional verification and synthesis, while providing a fully automated, and simple use-model. It brings together three powerful Apps, in a single product that all leverage the OneSpin Formal Platform, to driving three different verification perspectives:

  • Structural Analysis: Focused syntactic and semantic analysis of source code
  • Safety Checks: Exhaustively verify the absence of common sequential design operation issues and failure debugging
  • Activation Checks: Ensures that specific design functions can be executed and are not blocked by unreachability


DV-Inspect Flow


The three apps have one thing in common, they are all fully automatic and require no assertions to be created by the user. As such, DV-Inspect is a push button, automated tool that performs a powerful and complete range of verification functions without the need to learn how to write stimulus, create assertions or understand the formal mechanisms employed. This makes it an invaluable tool for designers to weed out possibly complex design bugs in their code with minimal operational overhead, early in the design process.

OneSpin 360 DV-Inspect is an invaluable tool for designers and other engineering specialization to discover and solve problems with minimal effort. The tool replaces a substantial amount of simulation by examining code operation for known classic problems, through an exhaustive analysis of source code.


DV-Inspect Inspection Examples


Key Features and Benefits

  • Integrates easily into existing design flows
  • VHDL, Verilog, SystemVerilog, SystemC or C++ supported
  • Assertion synthesis is leveraged to generate comprehensive structural test sets and coverage analysis, further improving quality
  • Debug tool with simulation trace generator makes understanding issues easy
  • Share computationally heavy tasks over a network
  • Advanced debugging
  • Assertion synthesis for RTL clean-up
  • Assertion synthesis for code coverage