Formal assertion checking has traditionally been hard to adopt, and has been viewed as a tool for specialists only. This has significantly changed with automation of recurring verification tasks using formal apps, as well as the widespread adoption of assertion languages, and vastly increased capacity of formal tools. Today a huge number of point tools for formal verification is available, each covering different formal use models.
OneSpin 360 DV-Verify goes beyond that by providing a unified, coverage-driven assertion-based verification flow, and including a full verification app library, as well as means for easy design exploration, all in one tool.
Introducing 360 DV-Verify
DV-Verify can be employed as a fully functional, coverage driven Assertion-Based Verification (ABV) capability, a design exploration, “what-if” analyser, and an automated, targeted problem solver. It has been designed to augment existing verification environments, enabling the discovery of bugs elusive in simulation-only solutions, while providing an extreme ease-of-use experience.
DV-Verify may be utilised in multiple stages of the Design Verification flow. OneSpin 360 DV-Verify is the only unified, coverage-driven assertion-based verification system available today that comes complete with a full App library for multiple use models.
- Agile Design Exploration: Early validation of design operations without writing stimulus for quick design iterations
- Metric-Driven Assertion-Based Verification (ABV): Comprehensive assertion-based verification with unique observation coverage
- Quantify Fault Observation Coverage: Effective measure of verification progress and coverage improvement
- Block Integration Validation: Scalable integration verification and functional analysis using automated flows
- OneSpin Formal Apps Library: Library of automated functions targeting recurring verification tasks
OneSpin 360 DV-Verify is a powerful and flexible capability that significantly reduces verification time and effort in multiple phases of an IC development project. It is a complete tool that is easy to use alongside existing simulation-based flows.
Key Features and Benefits
- Integrates easily into existing design flows
- VHDL, Verilog, SystemVerilog, SystemC or C++ supported
- SVA, PSL and OVL are supported
- Ease of set-up
- Advanced debugging tools including a structural assertion debugger, waveform debugging and source code analysis
- The ability to compile with standard RTL behaviour or without X-Optimisation
- Formal coverage analysis for metric-driven assertion-based verification
- Share computationally heavy tasks over a network