For safety-critical and high-reliability applications, Precision Hi-Rel offers industry’s most comprehensive Single Event Effects (SEE) mitigation strategies. And, integration with FormalPro provides assurance that synthesis-based mitigated design is functionally equivalent to the RTL, ensuring DO-254 certification.
Triple Modular Redundancy (TMR)
TMR is the most popular mitigation strategy used for protection from SEUs/SETs in FPGAs. Precision Hi-Rel provides the widest selection of TMR modes - LTMR, DTMR, GTMR & intelligent Selective TMR (iSTMR), enabling users the trade-off between safety, area, and performance. Inserting TMR at the synthesis level provides greater user control and superior Quality of Results (QoR).
Precision Hi-Rel offers two enhanced safe FSM modes:
- SEU Detect - detects invalid transition/state and recovers to a known state
- SEU Tolerant - absorbs an SEU and continues operation without interruption
With seamless integration in the synthesis flow and full user-control, it allows designers to implement these FSM optimizations globally or at a modular level.
Equivalence Checking with FormalPro
FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.
- Broad FPGA device support
- SEU and SET mitigation across a wide spectrum of FPGA resources
- Multiple TMR configurations - LTMR/DTMR/GTMR/iSTMR
- Error detection and Error correction FSM inference for all encoding types
- Single-bit error detection across design modules
- Inference of ECC RAM modes from RTL
- Formally verifiable TMR and Safe FSM
- Configurable mitigation solution with controls from global to leaf level
- Area optimization solutions for TMR mitigation
- Intelligent synthesis enabling mitigation insertion with optimal QoR