The Questa Verification Solution

OVERVIEW

The Questa Verification Solution transforms verification, dramatically increasing verification productivity and managing resources more efficiently built on several powerful technologies and tightly integrated with Veloce emulation Questa answers the challenges of increasingly complex SoCs.



Questa automates verification and debug of complex SoCs and FPGAs, dramatically increasing productivity and helping companies manage resources more efficiently. Questa best-in-class technologies maximize the effectiveness of verification at the block, subsystem, and system levels.





Questa Advanced Verification Products

The key to verification success is to decompose the problem and use the best solution for each aspect of the system. This places tremendous importance on the verification plan and the ability to collect metrics throughout the process and across all verification tasks to track progress against the plan, allocate and manage resources efficiently, and identify trends as the project progresses against schedule.



Questa Advanced Simulator logo

Questa Advanced Simulator

The core simulation and debug engine of the Questa Verification Solution; the advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

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Questa CDC Logo

Questa Clock-Domain Crossing

Questa CDC verification solutions focus on the interaction between clock or reset domains that cannot be handled using simulation-based verification techniques.


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Questa Formal Verification logo

Questa Formal Verification


The Questa Formal Verification tool complements simulation-based RTL design verification by analyzing all possible behaviors of the design to detect any reachable error states.


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Questa Verification IP logo

Questa Verification IP

Questa Verification IP improves quality and reduces schedule times by building protocol and methodology reusable components that support many industry standard interfaces.

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Questa inFact logo

Questa inFact

The industry’s most advanced portable stimulus testbench automation solution, achieving coverage goals 10 to 100X faster than constrained random testing and scaling across all design levels.

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Key Benefits

  • Integrates multiple point tools into flexible, open flows that integrate a broad arsenal of verification solutions
  • Decomposes the problem and employs the best solution, such as CDC verification, formal verification or mixed-signal simulation, to resolve it
  • Delivers high performance/capacity debug tightly integrated with the Visualizer Debug Environment
  • Increases your ability to build a verification plan and collect metrics to track its progress, allocate and manage resources efficiently, and identify trends as the project progresses against schedule