Designers use advanced multi-clocking and reset signal distribution architectures to meet high performance, low latency and low power requirements. Questa Clock-Domain Crossing (CDC) and Reset-Domain Crossing (RDC) tools focus on interactions between clock- or reset-domains that cannot be dealt with using simulation-based verification techniques.
Questa Clock-Domain Crossing Solutions
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock-domains does not accurately capture the timing related to the transfer of data between clock-domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.
Questa CDC Solutions identify errors that have to do with clock-domain crossings – signals (or groups of signals) that are generated in one clock-domain and consumed in another. It does so with structural analysis and recognition of clock-domains, synchronizers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation this technology can be used to inject metastability into functional simulation to verify the DUT correctly processes asynchronous clocks.
Questa Clock-Domain Crossing
Questa CDC finds errors using structural analysis to detect clock-domains, synchronizers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.
Questa Reset-Domain Crossing
Questa RDC formally verifies reset-domain crossings to exhaustively identify reset-domain crossing issues in SoC and system designs.
Questa Signoff CDC
Questa Signoff CDC automatically generates and analyzes assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.
- Questa CDC automatically identifies your clock and clock distribution strategy, minimizing set up time. Simply read in your RTL design and Questa CDC will pinpoint all potential CDC issues – no testbench is required.
- Questa CDC supports Synopsys Design Constraints (SDC) format constraints for clock and port domain settings and includes a TCL scripting environment with powerful control and reporting capabilities
- Fewest false negatives in the industry, so you don’t waste time chasing non-issues.
- CDC-centric analysis and debugging GUI leverages familiar schematics and waveforms where appropriate.
- Reuses your UPF file without modification to ensure low power circuitry does not introduce CDC-related issues.
- Questa CDC's high performance analysis can process 100-million-gate designs and its hierarchical capabilities enable unlimited capacity.
- Patented, automated metastability injection is the only way to find complex CDC reconvergence bugs.
- Automatic coverage reporting for CDC protocol and reconvergence verification (via UCDB) enables you to measure CDC verification progress and the quality of the testbench with respect to CDC protocols, and effectively manage the overall verification process.