Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyses code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.
Automated Intent-Focused Verification for Designers
Questa Design Solutions works with you from design creation through completion with a minimal set of additional inputs. Nothing more than RTL is required, except for UPF and basic constraints, when necessary.
Questa Design Solutions Tools
Questa Design Solutions tools are built on a consistent foundation with a common debug and user interface, producing designs that are correct-by-construction, proving designs meet the designer’s intent and the project’s quality requirements, and protecting the design throughout its development.
Questa Lint provides adaptive, integrated insight to the designer to ensure that the quality requirements and intent are met. Pre-configured methodologies provide immediate, intuitive feedback on design issues.
A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, AutoCheck makes it possible to eliminate a wide range of bugs without a testbench.
Questa X-Check is an automated application that exhaustively roots out ‘X’ issues without a testbench.
Questa Clock-Domain Crossing
Questa CDC finds errors using structural analysis to detect clock-domains, synchronisers, and low power structures via the UPF. It then generates assertions and metastability models for protocol and reconvergence verification.
Questa Reset-Domain Crossing
Questa RDC finds errors using structural analysis to detect asynchronous reset domains, synchronisers and low power structures via the UPF. It then generates assertions to exhaustively prove that the design is clean.
Questa Signoff CDC
Questa Signoff CDC builds on Questa CDC RTL analysis and automatically generates and analyses assertions to rapidly identify chip-killing glitches and other clock-domain crossing issues.
Questa Lint provides a fast check of your RTL, without waiting for a testbench, looking for completeness and consistency issues. Using syntactic, semantic, stylistic, and structural analyses, Questa Lint identifies issues at the time of introduction, preventing these issues from becoming expensive to fix later. Only issues that need to be fixed are reported, and the results are prioritised and collated such that the first issues addressed will provide the biggest return. Results are presented in intuitive visualisations, with metrics and quality scores summarising detailed information in an easy-to-use dashboard.
Architected to provide immediate out-of-the-box results, Questa Lint implements pre-configured methodologies for IP, FPGA or SoC development. Each of these methodologies offers an array of pre-defined readiness goals, such as floor-planning or synthesis readiness. In addition, there are pre-built checksets supporting industry standards such as DO-254, ISO-26262 or STARC. Once familiar with the tool, you can configure your own methodologies and checks to enable Questa Lint to enforce your development methodology, either through release-focused reviews or through continuous integration flows.
Questa Clock-Domain Crossing Solutions
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock-domains does not accurately capture the timing related to the transfer of data between clock-domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.
Questa CDC Solutions identify errors that have to do with clock-domain crossings – signals (or groups of signals) that are generated in one clock-domain and consumed in another. It does so with structural analysis and recognition of clock-domains, synchronisers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation this technology can be used to inject metastability into functional simulation to verify the DUT correctly processes asynchronous clocks.