Questa Verification IP (QVIP) improves quality and reduces schedule times by building reusable protocol and methodology components that support a wide range of industry-standard interfaces, eliminating the time spent developing and maintaining custom BFMs, verification components, or VIP.
The best way to create a SoC is with design IP: blocks that connect to standard buses such as AMBA AXI or PCIe, or memory devices. How do you then check that your chip works correctly with the IP? You need to create stimulus that follows the protocol, but who has time to become an expert at each protocol? The best way to verify your design is with Verification IP that has deep knowledge of the protocol. Siemens QVIP is available for a wide range of protocols such as AXI, AHB, PCIe/NVMe, Ethernet, USB, Serial, plus DRAM and Flash memories.
The Questa Verification Protocol Library includes an extensive range of ready-to-use protocols.
Fast and Accurate Memory Models
The Questa Verification Memory Library provides a complete memory verification IP library in one consistent industry-standard format, reducing the time it takes engineers to set up verification runs, enabling them to focus on verifying unique, high-value parts of their designs.