LeonardoSpectrum offers customers a well-proven, mature synthesis solution for both FPGAs and ASICs.

LeonardoSpectrum offers customers a well-proven, mature synthesis solution for both FPGAs and ASICs.


  • Mature synthesis tool for designing PLDs, FPGAs and ASICs, in VHDL or Verilog
  • Supports many current and legacy FPGA devices and ASIC families
  • Highly controllable advanced synthesis algorithms
  • Language neutrality, and both platform and target device independence


  • One tool, one easy learning curve, one set of scripts — for CPLDs, FPGAs, or ASICs
  • Provides high quality of results with the speed and features needed for large designs
  • True hierarchical support allows for easy grouping of design elements, enabling a single design to be partitioned across multiple devices
  • LeonardoInsight schematic viewer accelerates synthesis analysis
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Visualising RTL Design

With deep analysis capabilities, advanced creation editors, and complete project and flow management, HDL Designer delivers a powerful HDL design environment.

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FPGA Synthesis

Provides FPGA vendor-independent logic synthesis, offering reduced time to market, fewer design defects, and superior quality of results. The powerful optimisation engines, context sensitive GUI, …

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HDL Simulation

ModelSim’s award winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design.

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Simulation and Debug

Combines high performance and capacity simulation with unified advanced debug and functional coverage for the most complete native support of Verilog, SystemVerilog, VHDL, …

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High-Level Synthesis and Verification

Industry leading C++ / SystemC High-Level Synthesis with Low-Power estimation / optimization. Design checking, code, and functional coverage verification plus formal make HLS more than ….

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Requirements Management

Simplifies, automates, and enables requirements traceability from specification of the hardware specification through HDL coding, implementation, and validation.

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