Questa Advanced Verification


The Questa verification solution continues to evolve in response to the growing complexity of SoC designs. The increasing software content and configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions.

Questa automates verification and debug of complex SoCs and FPGAs, dramatically increasing productivity and helping companies manage resources more efficiently. Questa best-in-class technologies maximise the effectiveness of verification at the block, subsystem, and system levels.

Questa Verification Solutions

The key to verification success is to decompose the problem and use the best solution for each aspect of the system. This places tremendous importance on the verification plan and the ability to collect metrics throughout the process and across all verification tasks to track progress against the plan, allocate and manage resources efficiently, and identify trends as the project progresses against schedule.

Questa is an assemblage of technologies, methodologies, and libraries for modern ASIC and FPGA designs.

QuestaSim Logo

Combines high performance, high capacity simulation with unified debug and functional coverage for complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM.

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Questa Design Solutions

Automated and integrated suite of verification tools that analyses code at the design stage to detect bugs early, where they are cheapest and easiest to fix.

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Questa Formal Verification

User-friendly automated formal applications simplify the process of identifying and resolving bugs, eliminating the need for specialized formal expertise.

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Questa Visualizer

High-performance, high-capacity context aware debugger that supports a complete logic verification flow, including simulation, emulation, and prototyping.

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Questa Verification IP

QVIP improves quality and reduces schedule times by building protocol and methodology reusable components that support many industry standard interfaces.

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Questa Verification Management

A shared platform and environment for comprehensive verification management of design process, tools and data within a scalable, modular solution.

Key Benefits

  • Integrates multiple point tools into flexible, open flows that integrate a broad arsenal of verification solutions
  • Decomposes the problem and employs the best solution, such as CDC verification, formal verification or mixed-signal simulation, to resolve it
  • Delivers high performance/capacity debug tightly integrated with the Visualizer Debug Environment
  • Increases your ability to build a verification plan and collect metrics to track its progress, allocate and manage resources efficiently, and identify trends as the project progresses against schedule
QuestaSim Logo
Simulation and Debug

Combines high performance and capacity simulation with unified advanced debug and functional coverage for the most complete native support of Verilog, SystemVerilog, VHDL, …

Catapult Logo
HLS and Verification

Industry leading C++ / SystemC High-Level Synthesis with Low-Power estimation / optimization. Design checking, code, and functional coverage verification plus formal make HLS more than ….

Static RTL Bug Hunting

A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, Inspect makes it possible to eliminate a wide range of bugs without a testbench.

Questa CDC Logo
CDC Verification

Questa CDC finds errors using structural analysis to detect clock-domains, synchronisers, and low power structures via the UPF. It then generates assertions and metastability models for …

Questa Lint Logo
Static RTL Verification

Questa Lint provides adaptive, integrated insight to the designer to ensure that the quality requirements and intent are met. Pre-configured methodologies provide immediate, intuitive feedback …

Veloce proFPGA Logo
Hardware-Assisted Verification

The Veloce proFPGA system architecture offers best-in-class modularity, scalability, flexibility and portability to serve the verification requirements of today’s hardware and software engineers.

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