Questa Visualizer Debug

Visualizer provides a high performance/high capacity debugger that scales from simulation to emulation. Multiple automated features quickly find RTL, gate-level, and protocol bugs. On top of this intuitive foundation, there are powerful features that elucidate the design and its functionality.

Introducing Questa Visualizer

Debug is one of the most important verification technologies and is critical for achieving productivity in today’s complex designs. According to the 2018 Wilson Research Group Verification study, design and verification engineers now spend almost 40% of their overall project time debugging — and that percentage is growing.

Companies need debug tools that provide maximum performance, capacity and automation for the complete system-on-chip design and verification cycle.

Visualizer has several features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification. It provides a full set of synchronised views for analysing waveforms, source code, and connectivity. On top of this intuitive foundation, there are powerful features that elucidate the design and its functionality. These include a time cone view, which automates the tracing and visualization of the cause of an event (such as an X) back to its source through multiple clocks, and biometric search, an easy way to search and highlight where a particular value occurs throughout the design.

RTL Debug

Class object handles from the driver in a UVM testbench. These are all the transactions that were sent from the sequencer to the driver. The Virtual interface is also shown, along with the transactions from the channel. Additionally the values displayed are colored according to the biometric searches that have been created.

Root Cause Analysis

The Questa Visualizer Debug Environment allows you to find unknowns (X values), trace an event back in time to the root cause of that event through multiple clock domains and find origins of unknowns using the Time Cone window.

Causality Tracing

Automatic fan-in display using signal highlight from a signal back to the next primary input or flip flop.

Physical Connectivity

The Logic Cone window allows you to explore the “physical” connectivity of your design, to trace signals that propagate through the design, and to identify the cause of unexpected inputs, by showing a graphic view of the RTL objects in your design.