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Accelerating FPGA and Digital ASIC Design


Efficiency and quality are both a question of overview, readability, extensibility, maintainability, and reuse, – and a good architecture all the way down is the answer. This applies to both Design and Verification.

Course Details

Location Live Online (Instructor-led)

Presenter Espen Tallaksen

Dates 4th Nov – 7th Nov 2024

Duration 08 00 – 12 00 GMT (4 half days)

Registration Fee £1,250


Digital design for FPGAs and ASICs has a huge improvement potential with respect to development time and product quality. A lot of time is wasted on inefficient design, lack of awareness around this, and knowledge of the most critical digital design issues. This also seriously affects the quality of the end product. The good thing is that this huge improvement potential can be realised just by making a few important changes to the way we design.

The main focus of this course is quality and efficiency improvement, making you a better designer and your company a better product development organisation. 80-90% of the course is HDL independent. VHDL is used where code examples are needed, but most of this will be directly transferable to Verilog or SystemVerilog.

The most important design issues to improve are:

  • Design Architecture & Structure
  • Clock Domain Crossing
  • Coding and General Digital Design 
  • Reuse and Design for Reuse
  • Timing Closure
  • Quality Assurance – at the right level 

See the complete course description here

Course Objectives

The main goal of this course is to show how you can develop a far better FPGA/ASIC design – especially with respect to design overview, architecture, readability, extensibility, maintainability and reuse – resulting in better quality and faster development. Additionally, typical pitfalls will be covered – with a special focus on timing, synchronization, resets and clock domain crossing.

Target Participants

The course is intended for FPGA designers and Digital ASIC designers who want to work smarter and more efficiently – and design products with higher quality. Participants should have a good knowledge of FPGA development. Less experienced designers will also benefit significantly from this course, but will have less relation to the critical aspect of FPGA Development Best Practices. Previous participants have had from 1 year to 30 years of experience.


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