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Advanced VHDL Verification – Made simple


Learn the fastest growing VHDL Verification Methodology world-wide from the creator and main architect of UVVM.

Efficiency and quality are both a question of overview, readability, extensibility, maintainability, and reuse, – and a good architecture is the answer. This applies to both Design and Verification.

Course Details

Location Live Online (Instructor-led)

Presenter Espen Tallaksen

Dates 22nd April – 26th April 2024

Duration 08 00 – 12 30 GMT (5 half days)

Registration Fee £1,850


On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is a 5 half-days course on how to reduce development time and at the same time improve the quality.

The main differentiators between this and other similar courses are the focus on simplicity and the very structured approach to reuse – also inside a single project. We have seen and heard of many complex testbenches by various designers. A major problem with most of these testbenches seems to be that it gets too complex for everybody apart from the VHDL expert who designed it, – sometimes a person with a far more than average interest in the language or system details.

This course contains a general introduction to modern verification methodology and to UVVM (Universal VHDL Verification Methodology) – the world-wide fastest growing VHDL-FPGA verification methodology, and also the fastest growing verification methodology independent of HDL.

This course is based on the principles of ‘maximum cohesion & minimum coupling’ and ‘Divide and Conquer’, where the test case writer doesn’t have to know anything about the testbench implementation details, and the testbench implementer has a structured architecture all the way down. This approach to VHDL testbenches typically leads to man-hour savings of 20% – 60% and more, and is unique for this course.

See the complete course description here

Course Objectives

The main goal of this course is to show how you can achieve a far better testbench overview, readability, extensibility, maintainability and reuse – resulting in better quality and faster development.

  • Overview: So that anyone can easily understand the overall structure – just like a simple block diagram
  • Readability: So that anyone can read the test driver and from that understand exactly what is going on
  • Extensibility: Allowing fast and simple testbench changes to check new design modules and functionality
  • Maintainability: Allowing fast and simple testbench changes to adapt to design changes
  • Reuse: Between modules in a project; From modules to top-level in a project; From one project to another

After the course, participants will know how to structure an FPGA verification platform, how to implement their testbenches, and how to write test sequencers, which can be understood by software and hardware developers. Participants will also learn how to use the complete VHDL-based UVVM verification platform within their own organization

Target Participants

The course is aimed at FPGA designers and verification engineers with a good knowledge of VHDL and some experience with VHDL testbenches and verification. You should also have working knowledge with Questa, ModelSim, Riviera-PRO, Active-HDL or other simulator.

(The course if equally relevant for ASIC designers using VHDL for verification).


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