Systematic design errors, introduced by automated design refinement tools, such as synthesis, can be hard to detect, and damaging if they make it into the final device. Formal Equivalence Checking (EC) has been used for ASIC design flows for many years. As FPGAs become bigger and critical system components, exhaustively verifying the functional equivalence of Register Transfer Level (RTL) code to synthesized netlists and the final placed & routed FPGA designs is mandatory.

Introducing Questa Equivalent FPGA (FKA 360 EC-FPGA)

360 EC-FPGA is an automatic sequential equivalence checking tool that provides a fast and efficient method to ensure that aggressive synthesis optimizations have not introduced systematic errors that could disrupt the final design.

A major benefit of 360 EC-FPGA is to ensure that advanced FPGA synthesis optimisations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce functional errors. It supports all sequential synthesis optimisations performed in FPGA design flows. It verifies whole-chip, flat netlists, allowing for the most aggressive optimisations to be leveraged.

360 EC-FPGA verifies the optimised design ‘as is’ without gate-level simulation, design modifications or design restrictions, such as disabling synthesis optimisations. It eliminates the need for extensive scripting and many ‘side files’ generated by synthesis tools, providing a greater level of independence from the synthesis process.

The tool is “self-starting” by providing automated setup capabilities that detect mapping information, clocks and resets, and other initialisation settings. An advanced debugger is also included, which displays mismatches both directly in source and schematic windows, as well as through generated waveform traces.

360 EC-FPGA follows a conventional EC verification flow: design setup, mapping and comparison, and optional debug. However, the underlying sequential equivalence checking technology utilised in 360 EC-FPGA, which makes use of the OneSpin formal property checking engines, eliminates many of the design restrictions necessary with other solutions, as follows:

Industry Support

Support for all major FPGA devices, including (but not limited to):

We see the introduction of EC for FPGA to be an important addition for the validation of safety critical applications using programmable devices. As well as providing an exhaustive check, EC will identify errors quickly with the minimum of debug.