Visualizer has several features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification. It provides a full set of synchronised views for analysing waveforms, source code, and connectivity.
Debug is one of the most important verification technologies and is critical for achieving productivity in today's complex designs. Companies need debug tools that provide maximum performance, capacity and automation for the complete system-on-chip design and verification cycle.
More complex designs that include more software create new requirements for block-to-system verification reuse and the need for system verification and debug. To avoid wasting cycles at the system level, it is critical to identify bugs as early as possible and improve debug productivity.
Visualizer is a high-performance, high-capacity context-aware debugger that supports a complete logic verification flow, including simulation, emulation, and prototyping as well as design, testbench, low-power, and assertion analysis.
Class object handles from the driver in a UVM testbench. These are all the transactions that were sent from the sequencer to the driver. The Virtual interface is also shown, along with the transactions from the channel. Additionally the values displayed are colored according to the biometric searches that have been created.
Root Cause Analysis
The Visualizer Debug Environment allows you to find unknowns (X values), trace an event back in time to the root cause of that event through multiple clock domains and find origins of unknowns using the Time Cone window.
Automatic fan-in display using signal highlight from a signal back to the next primary input or flip flop.
The Logic Cone window allows you to explore the “physical” connectivity of your design, to trace signals that propagate through the design, and to identify the cause of unexpected inputs, by showing a graphic view of the RTL objects in your design.