Calibre Interfaces


The Calibre nmPlatform integrates with all major custom design tools, place and route systems, and a wide range of specialty design tools. Interfaces bring the power of Calibre sign-off engines to designers throughout the design flow, enabling early detection and correction of manufacturing issues.

Calibre Interfaces support integrations with custom, digital, and a wide range of specialty design tools. Designers can invoke Calibre verification from the design environment, quickly re-verify designs during chip finishing, and view, analyse, and debug results using the same interface across design tools, enabling designers to adopt a single verification solution, regardless of design style or methodology.

Calibre Interfaces

Deploying foundry verification decks to design flows is challenging. Calibre Interfaces enable designers to harness the power of Calibre sign-off engines in their design flows and to act on physical verification results quickly, improving designer productivity.

The Calibre RealTime Digital interface enables on-demand immediate Calibre DRC feedback for digital design flows, enabling P&R engineers to shave weeks off their tapeout schedule.

Calibre RealTime Custom

The Calibre RealTime Custom interface enables on-demand immediate Calibre DRC feedback for custom and analog/mixed-signal (AMS) design flows, improving DRC productivity by 2-4X.

Calibre RVE

The Calibre RVE results viewer provides fast, flexible, easy-to-use graphical debugging capabilities that minimise your turnaround time and get you to “tapeout-clean” on schedule.

Calibre Interactive

The Calibre Interactive interface is the invocation GUI for Calibre physical and circuit verification and parasitic extraction engines, with easy access from within popular layout design environments.

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Simulation and Debug

Combines high performance and capacity simulation with unified advanced debug and functional coverage for the most complete native support of Verilog, SystemVerilog, VHDL, …

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HLS and Verification

Industry leading C++ / SystemC High-Level Synthesis with Low-Power estimation / optimization. Design checking, code, and functional coverage verification plus formal make HLS more than ….

Static RTL Bug Hunting

A fully-automatic formal bug hunting app that finds deeply hidden bugs due to common RTL coding errors, Inspect makes it possible to eliminate a wide range of bugs without a testbench.

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CDC Verification

Questa CDC finds errors using structural analysis to detect clock-domains, synchronisers, and low power structures via the UPF. It then generates assertions and metastability models for …

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Static RTL Verification

Questa Lint provides adaptive, integrated insight to the designer to ensure that the quality requirements and intent are met. Pre-configured methodologies provide immediate, intuitive feedback …

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Hardware-Assisted Verification

The Veloce proFPGA system architecture offers best-in-class modularity, scalability, flexibility and portability to serve the verification requirements of today’s hardware and software engineers.

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